This compares to an x86 with MMX & SSE vector processing as follows:
AltiVec
32 separate Registers
128 bits per register
No interference with FP registers
No context or mode switching
Max throughput: 8 Flops / cycleMMX & SSE
8 MMX registers shared with the FPU, 8 for SSE
64 bits per mmx register, 128 bits per xmm register
MMX stalls the FP registers
Context switching required for MMX
Max throughput: 2 Flops / cycle
Therefore, a comparison of the rated speed of a CPU is not a complete assessment. The width of the CPU registers need to be considered. AltiVec enables "vector" processing, a streamlined set of calculations that fit neatly into the AltiVec's registers. AltiVec can process 8 x 32-bit instructions in one clock cycle:
2.3 GHz CPU * (8 floating point ops/cycle) * (2 processors) = 36 GFLops... with realworld application depending upon how well the code 'vectorizes'.
In addition, there is consideration for the quantity and size of the CPU cache, onboard memory that talks directly the CPU and holds calculations very close to the processor so that they can be used repeatedly without having to reach beyond the CPU itself. If a calculation must rely upon RAM, the process is slowed. If a calculation must deposit or draw from the hard drive, the process is significantly slowed and performance drops noticeably.
PowerPC G4s offer three levels of cache onboard the CPU. The 3rd cache is large and helps significantly in the PowerPC's ability to out-perform its x86 "equivalent".
AltiVec Resources
The following offer a deeply technical set of resources for understanding and programming with Motorola's AltiVec parallel processor:
Apple Developer Connection:
developer.apple.com/hardware/ve/
Motorola AltiVec Site:
www.motorola.com/altivec/
AltiVec.org:
www.simdtech.org/
