Tech blog October 2, 2015
This post is a part of a joint effort. A more simplified look at the inner workings of NAND can be found?here.
Flash memory technology (both NOR and NAND type) was invented by Dr. Fujio Masuoka at Toshiba in the 1980s.
?NAND flash cells are a variant of the MOSFEST transistor (Image 1 below) with a floating gate added below?the original control gate. The MOSFET transistor works by having the control gate dictate?the flow of voltage like an on/off switch. By applying voltage to the control gate, a conductive channel can be made to appear between the source and the drain (between N+ and N+ in the image), allowing voltage to flow through the transistor(the equivalent to being "on"). When no voltage is applied to the control gate, the area marked P stays insulated and no electricity flows, resulting in an "off".
The MOSFET transistor is the basis for most electronics in use today; the binary on/off makes them extremely versatile. Source: Wikipedia
To make a NAND cell, the architecture remains the same as a MOSFET, but with the simple addition of?an electronically isolated gate ?(known as the floating gate) below?the control gate (image 2). Because?it is electronically isolated, the floating?gate is able to hold a charge indefinitely, thus allowing data to be recorded without fear of losing that data. The data that is recorded is represented by the voltage left lingering within the floating gate.
Same basic layout of the MOSFET but with an added transistor. Source: Wikipedia
Introducing electricity into an isolated area is a bit tricky, so voltage is channeled?and drained from the floating gate using Fowler-Nordheim tunneling, also known as quantum tunneling (image 3). The basic idea is that?quantum tunneling?allows charges to pass through an insulated barrier (the oxide layer). The introduction of electricity into the floating gate is the basic premise as to how data is recorded onto these cells.
The blue portion of this image is the charge getting exponentially smaller and being able to pass through the barrier. Source: Wikipedia
How NAND Is ReadWhen a charge is applied to the control gate, the floating gate screens (partially cancels) the electric field, which?increases the threshold voltage ,which then must be applied to the control gate to make the transistor conduct.?Because the floating gate partially cancels the electric field from the control gate when the floating gate has a charge, the amount of electricity needed to reach threshold (remember, threshold is the amount of electricity needed to attain conductivity throughout the cell like in a traditional MOSFET) is then increased. NAND cells are then read in a “test-and-see” fashion. This m eans that in order to get a specific cell read, the controller would apply an intermediate (in-between) voltage and test the reaction. If no conductivity is reached, then it is determined that the floating gate has a charge (remember: if the floating gate has a charge, it cancels some of the voltage from the control gate) and is therefore a logical “0”. If the intermediate voltage does indeed cause the ce ll to conduct, it is determined that the floating gate is empty and thus a logical “1”. It is in this fashion that NAND flash is able to be read.
?There are two ways to organize the floating gate transistor arrays which constitute flash memory: NOR and NAND.
?In NOR flash, the cells (containing the floating-gate transistors and supporting circuitry) are connected individually to the 'bit lines', which is the output of the cells. This arrangement makes it possible to address individual cells, i.e. bits. Usually the reading of the flash content happens in bytes: this makes it possible to use the NOR flash as a truly Random Access device, i.e. all bytes are addressable individually. When NOR flash is equipped with an address and data bus, for the CPU it appears as a RAM device, and as such provides in-place execution: there's no need to copy the content of the NOR flash into RAM in order to execute (machine) code contained in it. For examle, Flash BIOS is made of NOR flash: the CPU can execute the initial boot code stored in it directly.
?Although NOR flash organization is conceptually simple, it requires considerable amount of resources on the die: all cells have to be connected to the bit line(s) individually.
NOR has a much lower latency when compared to NAND. Source: Wikipedia
NAND FlashIn NAND flash, the cells aren't connected individually to the bit line, but rather they're connected serially to each other. This organization uses less resources on the die: for the same amount of storage, NAND flash uses approximately 60% less die area than if it was built as NOR flash.
?There's nothing inherent in the organization of NAND flash which would make it impossible to read or a single cell (bit); rather, the goal of NAND flash is to be simpler and smaller than NOR flash. The trade-off is between circuit complexity (as expressed in increased bit density in NAND vs. NOR) flash and the size of addressable elements (bytes in case of NOR flash, pages in case of NAND flash).
NAND cells only have one grounding interconnect and thus allow a greater density compared to NOR. Source: Wikipedia
SLC vs. MLC vs. TLC
Another way of increasing bit density is by storing more than one level of electric charge on the floating gate, and then applying multiple intermediate reading voltage levels. For example, two bits can be stored in a single cell if there are four distinct charges and corresponding read voltage levels are utilized; and if eight distinct charge and read voltage levels are used, three bits can be stored in a single cell. When a single bit is stored in each cell, it is called a Single-Level Cell (SLC) device. When there's more than one bit is stored in a cell, it is called a Multi-Level Cell device, which includes Triple-Level Cell devices storing three bits in each cell. You can read more about the pros and cons of these SSD's in our other article
Error Correcting Code
Decreasing feature sizes in the manufacture of NAND flashes and multiple-level cells (MLC) both makes it more likely that cells fail: either because the charge level changes in them (for example due to so-called read disturb errors) enough that the reading process leads to distorted bit values, or that the erasing process fails to drain all charge from the floating gate. As far as the first type of failure (reading of the correct stored value) goes, error correcting codes (ECC) are utilized in NAND flashes. For SLC NAND devices, usually Hamming codes are used for ECC. For MLC (including TLC) devices, Reed-Solomon codes and Bose-Chaudhuri-Hocquenghem codes are commonly used ECC.?
Editor note: We'll be taking a deeper dive into ECC, TRIM, and Garbage Collection in the upcoming post.
Article by: Andras Kovacs & Israel Imru